1. Field of the Invention
Embodiments of this invention relate generally to processors and processing circuits, and, more particularly, to a method and apparatus for a floating point multiply accumulator (FMAC) multi-precision mantissa aligner.
2. Description of Related Art
Processors and processing circuits have evolved becoming faster and more power intensive. With increased speed and capabilities, processors and processing circuits must be adapted to be run more efficiently and with greater flexibility. As technology for these devices has progressed, there has developed a need for performance and efficiency improvements. However, complexity, power and performance considerations introduce substantial barriers to these improvements. Additionally, circuit area and circuit overhead requirements (e.g., routing and layout) provide barriers to improvements.
Multi-precision mantissa alignment may alleviate or reduce the abovementioned barriers to power reduction, efficiency and flexibility. In modern implementations for FMACs, support for two parallel single-precision operations embedded in a higher precision datapath is not found. State of the art FMACs are thus incapable of improving power usage, overhead, efficiency and flexibility through the use of parallel single-precision operations.